1. Field of the Invention
The present invention relates to a gallium arsenide static induction transistor, and more particularly it pertains to a normally-off type gallium arsenide static induction transistor which is suitable for use in, for example, low and medium power operation in, for example, integrated circuits.
2. Brief Description of the Prior Art
A static induction transistor (SIT) has a structure resembling that of a known field effect transistor. However, the static induction transistor differs greatly from known field effect transistors in that width and impurity concentration of the channel region of an SIT enables formation of a potential barrier within the channel region by the built-in potential of the gate region and the potential applied to this gate region. The potential barrier can be present during conduction by the transistor. The location within the channel region at which the potential barrier is produced is called intrinsic gate.
In a static induction transistor the height of the potential barrier at the intrinsic gate is controlled not only by the gate potential but also by the drain potential. The control of the potential barrier height by variations of the drain currents, in the SIT, is provided by making the effective resistance between the source electrode and the intrinsic gate very small.
Gallium arsenide has pronounced features of a very high electron mobility and a wide energy gap as compared with those of silicon. The manufacturing processes of gallium arsenide devices, however, typically have not been exploited. Thus, it is desirable that a gallium arsenide transistor, particularly when it is employed in an integrated circuit, have a simple structure.